Dec 01, 2018 · This video has been made for VLSI students for knowing how to make layout design on Mentor graphics. It is a long video due to many gaps and waits, which can be skipped or fast forwarded. The Synopsis and Mentor Graphics EDA tools are used for VLSI implementation and veriﬁcations of the adder architectures. Synopsys Design Vision and PrimeTime are used for front-end synthesis and timing analysis, while the Synopsys ICC is used for backend layout generation. Simulation is performed using Synopsys VCS, while DRC, LVS, and PEX are Your cadence window should open when you run 'virtuoso' and you should have several FinFET transistor "flavors" and several sample cells, including an inverter and a flip-flop that you should be able to simulate, run DRC, LVS and PEX, etc. With this you have finished the ASAP7 pdk setup, congrats!